(1) Field of the Invention
The invention relates to a method of copper metallization in the fabrication of integrated circuits, and more particularly, to a method of reducing the formation of copper hillocks in copper metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. Because of its lower bulk resistivity, Copper (Cu) metallization is the future technology for feature sizes of 0.18 microns and below. Often, a damascene or dual damascene process is used to provide Cu metallization. The copper is deposited within the damascene opening and polished back. Then, a capping layer, such as silicon nitride or silicon carbide, is deposited over the copper plugs to prevent copper from diffusing into overlying layers.
Typically, before the capping layer is deposited, the wafer is heated to stabilize the wafer temperature. A coating of the capping layer material on the deposition chamber walls releases NHx-related molecules that react with copper to cause Cu hillock generation. Cu hillocks are also caused by exposing the wafers to NH3 gas in the ambient of the deposition chamber. Copper hillocks reduce copper reliability and confuse defect inspection tools. Reduction of copper hillocks in the copper damascene process becomes more and more important for yield and reliability improvement. It is desired to reduce copper hillock generation in the copper metallization process.
U.S. Pat. No. 5,714,418 to Bai et al discloses a capping layer of nitride over copper, then an oxide layer. U.S. Pat. No. 5,612,254 to Mu et al a silicon nitride layer over copper. U.S. Pat. No. 5,654,232 to Gardner teaches a copper damascene process. U.S. Pat. No. 5,589,233 to Law et al shows a chamber pre-coat process. None of the references discusses Cu hillock prevention.
A principal object of the present invention is to provide an effective and very manufacturable method of reducing copper hillocks in a copper metallization process in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method for reducing copper hillocks by reducing copper oxide formation.
A further object of the invention is to provide a method for reducing copper hillocks by pre-coating the deposition chamber with an oxide layer.
A still further object of the invention is to provide a method for reducing copper hillocks by using NH3 plasma rather than NH3 gas for CuO reduction after copper chemical mechanical polishing (CMP).
Yet another object of the invention is to provide a method for reducing copper hillocks by reducing the time between copper CMP and capping layer deposition to less than one day.
Yet another object of the invention is to provide a method for reducing copper hillocks by reducing the time between copper CMP and capping layer deposition to less than one day, pre-coating the deposition chamber with an oxide layer, and using NH3 plasma rather than NH3 gas for CuO removal.
In accordance with the objects of this invention a new method of reducing copper hillocks in copper metallization is achieved. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by: coating the deposition chamber with an oxide layer, thereafter heating the wafer using NH3 plasma, and thereafter depositing a capping layer overlying the copper layer and the dielectric layer wherein the time lapse between polishing back the copper layer and depositing the capping layer is less than one day (24 hours).